High voltage mos devices with high gated-diode breakdown voltage and punch-through voltage

ABSTRACT

A method of fabricating CMOS devices suitable for high voltage and low voltage applications, while maintaining minimum channel lengths for the devices. In one embodiment, pocket implants ( 310 ) are formed in a minimum channel device causing a reverse channel effect. The reverse channel effect is optimized for the minimum channel length of the device. Field implants ( 120 ), enhancement implants ( 130 ), and wells ( 140 ) are all formed using a single mask.

[0001] This application claims the benefit of Provisional Patentapplication Ser. No. 60/024,927, filed Aug. 30, 1996, and ProvisionalPatent application Ser. No. 60/025,843 filed Sep. 6, 1996, both of whichare incorporated herein by reference for all purposes.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to integrated circuits, and moreparticularly to high voltage CMOS transistors.

[0003] A general trend in CMOS logic is to provide smaller transistorswith minimum feature sizes and lower power supply voltages. This scalingof CMOS transistors allows for the incorporation of more devices ontothe same area of silicon. It also allows for lower power operations andgreater reliability because the electric field is reduced. As the powersupply voltage is scaled down, peripheral requirements of thetransistors such as field isolation, junction breakdown voltages, andpunch-through voltages are also reduced.

[0004] However, some CMOS technologies, particularly those involvingnonvolatile memory such as EEPROM, EPROM, Flash, antifuse technologies,and the like, require the use of high voltages internally. For example,some programmable logic devices (PLDs) include nonvolatile memories thatuse high voltages for programming and erasing the memories. AlteraCorporation in San Jose, Calif. produces some exemplary PLDs with thischaracteristic.

[0005] Typically, these devices use high voltages ranging from about 9volts to about 16 volts. These high voltages are used for programmingand erasing the programmable memory cells. High voltages may also beused to improve the performance of the speed path of the integratedcircuit. The high voltage requirements of these technologies do notscale as easily as their counterparts in logic CMOS technology. Forexample, some of these technologies use the same 9 to 16 volt range ofhigh voltage to program and erase memory cells, even if the supplyvoltage is scaled down. Therefore, the requirements for high junctionbreakdown voltages, high transistor punch-through voltages, and highfield isolation voltages continue to exist even when the transistorfeature sizes are reduced.

[0006] In mixed-mode applications logic CMOS devices are integrated withnonvolatile CMOS memory devices. In these applications, simultaneoushigh voltage and low voltage requirements exist. These simultaneousrequirements are often contradictory. For example, high voltagetransistors with high junction breakdown characteristics and highpunch-through characteristics are needed to pass the high voltage. Atthe same time, in order to efficiently pass the high voltage from sourceand drain, without significant voltage drop, the transistor should havelow channel doping to minimize the so-called body effect. In previousgenerations of technology using looser design rules, these contradictoryhigh voltage requirements were met using long channel lengthtransistors. However, as the technology is scaled down to 0.35 μmeffective channel length (L_(eff)) and beyond, the cost and difficultyof integrating these high voltage transistors is increased.

[0007] As can be seen, there is a need for high voltage toleranttransistors and devices, especially for use in integrated circuits wherehigh voltages are used internally.

SUMMARY OF THE INVENTION

[0008] It is desirable to provide a technique for obtaining a set ofminimum channel length transistors in a CMOS technology for both highand low voltage use. The native high voltage transistors in the setshould preferably maintain high punch-through characteristics.Preferably, the transistors in the set will have the same minimumchannel length. Designing all the transistors in the set to the sameminimum channel length allows the design rules to be simpler, providesmatching devices, simplifies the modeling of the transistors, and allowslayout in a smaller area than long channel devices. It is desirable thatsuch technologies be useful for 0.35 μm effective channel length processtechnology and beyond. Further, the techniques to obtain these devicesare preferably implemented without using any additional masks.

[0009] Consequently, the present invention provides an improvedtransistor for an integrated circuit. The transistor comprises sourceand drain regions in a substrate defining a channel region between them.The source and drain regions are separated by a channel length. Aplurality of pocket implants, also known as “halo implants,” extend intothe channel region between the source region and the drain region tocause a reverse short channel effect for the transistor.

[0010] The present invention also provides a method of fabricating anintegrated circuit comprising the steps of depositing a field implant,depositing a well implant, and depositing an enhancement implant,wherein the steps of depositing a field implant, depositing a wellimplant, and depositing an enhancement implant are done using a singlemask.

[0011] A further understanding of the nature and advantages of theinventions herein may be realized by reference to the remaining portionsof the specification and the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1A shows a cross-section of a low voltage NMOS transistor;

[0013]FIG. 1B shows a cross-section of a low voltage PMOS transistor;

[0014]FIG. 2A shows a cross-section of a native NMOS transistor;

[0015]FIG. 2B shows a cross-section of a native PMOS transistor;

[0016]FIG. 3 shows a cross-section of a transistor with pocket implants;

[0017]FIG. 4 shows a cross-section of a transistor with merged pocketimplants;

[0018]FIG. 5 is a graph of the channel doping characteristics of atypical transistor with pocket implants;

[0019]FIG. 6 is a diagram of circuitry for use in a voltage pump usingtransistors of the present invention;

[0020]FIG. 7 is a diagram of circuitry for use in a memory usingtransistors of the present invention; and

[0021]FIG. 8 is a flow diagram of a technique for making a device of thepresent invention.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENT

[0022]FIG. 1A shows a cross-section of a low voltage NMOS transistor100. This transistor would be used in the implementation of typicallogic gates on an integrated circuit. Transistor 100 has source/drainregions 105 made of n+ material and a polysilicon gate region 110.Operation of such a device is well known to those of skill in the art.Transistor 100 includes field implants 120 adjacent to the edge of eachsource-drain region 105. In addition, an enhancement implant 130 isformed in a channel region 135 of the transistor. Enhancement implant130 is located close to the surface of the substrate and is used toadjust the magnitude of the threshold voltage V_(t) of the transistor tobe about 0.50 volts to 0.70 volts. The transistor also has a wellimplant 140 of p-type material to control the body doping concentrationof the device. An isolation region 150 electrically isolates individualdevices from one another.

[0023]FIG. 1B shows a cross-section of a low voltage PMOS transistor160. Source/drain regions 105 are implanted or doped with p+ ions, andwell implant 140 is of n-type material. As is well known to those ofskill in the art, the operational physics of a PMOS transistor is thecomplement of that used to describe the operation of an NMOS transistor.It is understood that the principles of the present invention apply toboth NMOS and PMOS type devices.

[0024] Typical enhancement transistors 100 and 160 may not be capable ofhandling the high voltages needed for some applications, such asinterfacing with non-volatile memory cells. When the gate voltage ongate 110 is low (i.e., zero volts), the breakdown voltage ofsource/drain region 105 is limited by enhancement implant 130 and wellimplant 140. On the other hand, when the gate voltage on gate 110 ishigh, the breakdown voltage is limited by field implant 120. Inaddition, if transistors 100 and 160 are used as high voltage passgates, the maximum amount of high voltage that can pass from drain tosource is limited by the body effect due to enhancement implant 130 andthe doping level of well implant 140. The doping level of well implant140 can be adjusted to control the punch-through resistance and thelatch-up immunity of transistors 100 and 160. Transistors 100 and 160may be optimized by controlling the properties of well implant 140,enhancement implant 130, and field implant 120.

[0025]FIG. 2A shows a cross-section of a native NMOS transistor 200.FIG. 2B shows a cross-section of a native PMOS transistor 250. It willbe recognized by one of skill in the art that the principles discussedin the present invention apply to both NMOS and PMOS transistors 200 and250. For simplicity, the term transistor will be used to apply to bothNMOS and PMOS transistors. In general, the term “native transistor”refers to a transistor is not implanted with the enhancement implant.The absence of the enhancement implant reduces the body effect of thetransistor. This results in the native transistor having a low V_(t),typically about 0 volts. The term “native translator” also refers to alow V_(t) transistor (e.g., V_(t) of about 0 volts to 0.2 volts) or atransistor with low channel doping.

[0026] Compared with a typical enhancement transistor 100, fieldimplants 120 in native transistors 200 and 250 are offset fromsource/drain regions 105. This offset allows native transistors 200 and250 to support a high drain breakdown voltage when the gate voltage ongate region 110 is high. The amount of offset between field implant 120and the source/drain regions 105 determines the maximum drain breakdownvoltage the device can support. When the offset is very large, the gateddiode breakdown voltage of the junction approaches that of a purejunction. The reduction or elimination of enhancement implant 130 alsoincreases the drain breakdown voltage at zero-volt bias on gate region110.

[0027] It is desirable to provide a transistor that supports high drainbreakdown voltage for any bias voltage on gate region 110. However,transistors 200 and 250 may not be practical for this purpose when thechannel length is scaled down. This is due to the fact that transistor200 is susceptible to source and drain punch-through as the voltagebetween source and drain increases. A partial solution to this is to usea longer channel length device. However, the use of a long channeldevice as technology is scaled down to 0.35 μm and beyond is costly dueto the extra space required for layout. Furthermore, modeling may becomemore difficult since separate models need to be generated for the longerchannel devices. In addition, native devices and transistors areavailable when separate V_(t) implant and field implant masks are in theprocess flow for a technology. However, the trend of using retrogradedwells, with implants through the field oxide, will not afford theseparate masking steps necessary to provide for native devices asdescribed.

[0028]FIG. 3 illustrates a cross-section of a transistor 300 with pocketimplants. Pocket implants, also known as “halo implants,” increase thepunch-through voltage of a transistor (native or enhancement). Pocketimplants may be formed of n-type material or p-type material. Typically,the pocket implant is of the opposite polarity from that of source/drainregions 105. Consequently, a PMOS transistor has n-type pocket implants,while an NMOS transistor has p-type pocket implants.

[0029] Transistor 300 is similar to native transistors 200 and 250 withthe addition of two pocket implants 310. Pocket implants 310 may beimplemented through large angle implantation. They surround thejunctions of source/drain regions 105. Pocket implants 310 may be ofn-type material or p-type material, depending upon whether transistor300 is a PMOS or NMOS transistor, respectively.

[0030] Pocket implants 310 are optimized in conjunction with lightlydoped drain (LDD) processing. Pocket implants 310 act to reduce thesubthreshold leakage current in the transistor since they effectivelyincrease the potential barrier height between source/drain regions 105and channel region 135.

[0031]FIG. 4 shows a cross-section of a high voltage transistor 400formed by the technique of the present invention. Transistor 400 hasgate region 110, and two source/drain regions 105 separated by a channelregion 135. An isolation region 150 separates transistor 400 from otherdevices in the integrated circuit. Field implants 120 are offset fromsource/drain regions 105 as described above. Mask region 410 is the maskarea defined for formation of well 140. Well 140, field implant 120, andenhancement region 130 (for enhancement transistors) can be formed byimplanting at different energy levels, using only the mask defining maskregion 140.

[0032] Transistor 400 also has two pocket implants 310 at the junctionsbetween channel region 135 and source/drain regions 105. However, incontrast with transistor 300 of FIG. 3 which has a long channel,transistor 400 has a short channel. As the channel length of transistor400 becomes shorter, pocket implants 310 begin to merge together. Themerging of pocket implants 310 cause the threshold voltage V_(t) oftransistor 400 to change. For some short channel lengths, as pocketimplants 310 merge, V_(t) is increased. This effect is known as a“reverse short channel effect.” This increase in V_(t) increases thepunch-through voltage over that of a long channel device.

[0033]FIG. 5 is a graph showing the channel doping profile of transistor400 and illustrates the reverse short channel effect. The graph plotsthe voltage threshold V_(t) against the effective length L_(eff) ofchannel region 135. As can be seen from the graph, at higher channellengths, V_(t) is relatively constant. However, as the channel lengthshortens and pocket implants 310 begin to merge, V_(t) becomes higherfor a short range before dropping off sharply. This area of higher V_(t)is due to the reverse short channel effect, and is shown in FIG. 5 asregion 510.

[0034] During the implantation of pocket implants 310, the amount oflateral diffusion can be adjusted to optimize the reverse short channeleffect for the technology being used. In the specific embodiment, thechannel length is 0.35 μm. As process technology improves, channellengths will likely become less than 0.35 μm, such as 0.25 μm, 0.18 μm,0.18 μm, 0.15 μm, 0.10 μm or even less. The principles of the presentinvention will be applicable in cases with shorter channel lengths.Therefore, in the specific embodiment, pocket implants 310 are optimizedsuch that the apex in region 510 of the graph is at the 0.35 μm channellength. In technologies with different channel lengths, the pocketimplants may be optimized accordingly.

[0035] Due to this reverse short channel effect, a configuration of twominimum channel length transistors (such as transistor 400) in serieswill offer a much improved punch-through immunity over a singletransistor with twice the minimum channel length. This allows both lowvoltage transistors and high voltage native transistors to be designedwith the same minimum geometry channel length for the given technology.

[0036] An example of a use for transistor 400 is in the design ofvoltage pumps. A voltage pump should be able to pass high voltages,without high leakage current. If the leakage current is high, then thevoltage pump will not be able to maintain the proper voltage, or pumpefficiently to the desired voltage. FIG. 6 shows typical circuitry foruse in a voltage pump design. The circuitry includes two transistors 400having the short channel length of the present invention and a capacitor610. Transistors 400 are connected in a diode fashion and placed inseries with one another. Capacitor 610 is coupled between the input tothe series of transistors 400 and a charging node 620. Typically, aninput pulse is introduced at charging node 620. Gradually, with eachsucceeding pulse, a high voltage node 630 is “pumped” to a desired highvoltage. Therefore, transistors 400 are subject to the stress of a highvoltage at high voltage node 630, and should be able to tolerate thestress.

[0037] Another use for transistor 400 is in memory cell design. Whenprogramming a memory cell, a word line WL is selected, allowing V_(high)to pass to a memory cell element. Leakage current is undesirable in thedesign of memory cells. FIG. 7 shows a diagram of a memory cell designusing two transistors 400 of the present invention. Transistors 400 areconnected in series between V_(high) and a memory cell element 710.Transistors 400 are commonly selected with WL. When WL is asserted,transistors 400 pass the high voltage to memory cell element 710.

[0038] Many other uses in integrated circuits for high voltagetransistors may be readily envisioned by one of skill in the art. Theabove examples illustrate the use of two transistors 400 in series.However, any number of transistors 400 may be strung together. The aboveexamples are given by way of example only, and not to imply anyparticular limitation.

[0039]FIG. 8 is a flow diagram showing a technique for fabricatingtransistors of the present invention. Although a specific embodiment isshown, many of the steps can be substituted or combined with otherfabrication techniques that are now known or may be developed in thefuture without departing from the spirit and scope of the presentinvention.

[0040] In step 810, isolation regions 150 are formed in the substrate.One purpose of isolation regions 150 is to electrically isolateindividual devices from other devices sharing the same substrate. Forexample, if an NMOS transistor and a PMOS transistor are adjacent toeach other, an isolation region may be formed between them to isolateone transistor from the other. Conductive layers are later formed tomake desired electrical connections. Isolation regions 150 may beformed, for example, by field oxidation, Shallow Trench Isolation (STI),or Local Oxidation of Silicon (LOCOS), or other techniques.

[0041] In step 815, p-type wells 140, field implants 120, andenhancement implants 130 are formed. In the specific embodiment, thethree types of implants may be done a common p-well mask. Of course, allthree implants are not necessary for all types of devices. For example,some native transistors do not have enhancement implant 130. Also, anNMOS transistor in a p-type substrate may not need a p-type well. Usinga single p-well mask, by varying the energy levels and dopants, any ofthe three elements are formed. Many different techniques may be used todo the actual implantation. For example, the p-well implant may be doneusing retrograde well implantation.

[0042] In step 820, the previous step is repeated with an n-well maskfor formation of n-type wells. An n-well mask is used in the formationof the n-type wells 140, field implants 120, and enhancement implants130 for PMOS type devices. Well 140, field implant 120, and enhancementimplant 130 may all be formed using the n-well mask.

[0043] After formation of the wells, a gate oxidation (not shown) isformed in step 825. The gate oxidation may be formed in one process stepfor a thin oxidation and two steps for a thick oxidation. After the gateoxidation is formed, in step 830, a polysilicon layer is deposited andpolysilicon gate region 110 is etched above the oxidation layer.

[0044] In step 835, n-type pocket implants 310 are formed for the PMOSdevices. Pocket implants 310 may be formed by implanting ions into thesubstrate using gate region 110 as a mask. The implantation ispreferably done at an angle. The implantation is laterally diffused tooptimize the reverse short channel effect of pocket implants 310. It isdesirable that the maximum V_(t) be provided for the channel length ofthe process being designed. Phosphorus, arsenic, or other n-type dopantsmay be used as the dopant for forming n-type pocket implants 310.

[0045] Also in step 835, the first implant of source/drain regions areimplanted may be completed. A light doping of p-type material is placedin the substrate using gate region 110 as a guide. This is the firststep in a procedure known as “lightly doped drain” (LDD) processing. LDDprocessing is well-known, and the details of this procedure will beunderstood by one of skill in the art. Though the specific embodimentuses LDD processing, other techniques may also be used that do not use amulti-step source/drain implanting process. In such cases, this portionof step 835 may be unnecessary.

[0046] In step 840, p-type pocket implants 310 are formed for the NMOSdevices. These are formed using gate region 110 as a guide andimplanting pocket implants 310 with a dopant. The implantation ispreferably done at an angle and laterally diffused to optimize thereverse short channel effect of the transistor. The dopant may be, forexample, boron. In the specific embodiment, an additional blanket boronimplant (with a preferred dose in the range of 10¹¹ cm⁻²) is used toincrease the channel doping of the native transistor. This provides agreater margin of punch-through immunity. The impact of this blanketboron doping on the p-channel transistors can be mitigated by slightlyincreasing the doping concentration of the n-well in step 820. Such atechnique will allow additional margin for transistor punch-throughimmunity. The first implant for LDD processing in the n-type devices isalso accomplished in this step.

[0047] In step 845, spacers (not shown) are placed next to the gate.These spacers may be used to mask off a portion of the first drainimplant. Then in steps 850 and 855, the n-type and the p-typesource/drain regions 105 are respectively formed with the second implantof the LDD process, using the gate with the spacers of step 845 as aguide.

[0048] Finally, in step 860, the contact metal layer is formed, followedby step 865 in which the via metal layer is formed. These steps are wellknown to those of skill in the art.

[0049] The specific embodiment described above is given as an exampleonly. It will be recognized by one of skill in the art that many of thesteps may be substituted with currently available or yet to bedetermined techniques without departing from the scope and spirit of thepresent invention. The claims are intended to be limited only by theattached claims.

What is claimed is:
 1. A transistor for an integrated circuit,comprising: a source region in a substrate; a drain region in thesubstrate; a channel region between the source and drain regions,wherein the source and drain regions are separated by a channel length;and a plurality of pocket implants extending into the channel regionbetween the source region and the drain region to cause a reverse shortchannel effect for the transistor.
 2. The transistor of claim 1, whereinthe plurality of pocket implants merge in the channel region.
 3. Thetransistor of claim 1, wherein the plurality of pocket implants merge ata midpoint in the channel length in the channel region.
 4. Thetransistor of claim 1, wherein the pocket implants are doped with adopant of opposite polarity from that used for the source and drainregions.
 5. The transistor of claim 4, wherein the source and drainregions are n-type, and the pocket implants are p-type.
 6. Thetransistor of claim 5, wherein the p-type pocket implants are formedwith a boron dopant.
 7. The transistor of claim 6, wherein the pocketimplants are further doped with a blanket boron implant.
 8. Thetransistor of claim 7, wherein a dosage of the blanket boron implant isabout 10¹¹ cm⁻².
 9. The transistor of claim 4, wherein the source anddrain regions are a p-type material, and the pocket implants are ann-type material.
 10. The transistor of claim 9, wherein the n-typepocket implants are formed with a phosphorus dopant.
 11. The transistorof claim 1, wherein due to the reverse short channel effect, thetransistor has a higher punch-through voltage.
 12. The transistor ofclaim 1, wherein the transistor is a native transistor.
 13. Thetransistor of claim 12 where in an enhancement implant is absent fromthe channel region.
 14. The transistor of claim 1 wherein the transistorhas a channel length about equal to a channel length of a logictransistor in the same substrate.
 15. The transistor of claim 1 whereinthe pocket implants are formed by implantation at an angle.
 16. Acircuit in an integrated circuit, comprising: first and secondtransistors coupled in series, each of the transistors comprising: asource region in a substrate; a drain region in the substrate; a channelregion between the source and drain regions, wherein the source anddrain regions are separated by a channel length; and a plurality ofpocket implants extending into the channel region between the sourceregion and the drain region to cause a reverse short channel effect forthe transistor.
 17. The circuit of claim 16, wherein a punch-throughvoltage for the series of transistors is greater than a punch-throughvoltage for a transistor with a channel length twice as long as thechannel length of the first and second transistors.
 18. The circuit ofclaim 16, further comprising a capacitor in series with the first andsecond transistor.
 19. The circuit of claim 18, wherein the circuit is avoltage pump.
 20. The circuit of claim 16, wherein the circuit is amemory cell.
 21. A method of fabricating an integrated circuitcomprising the steps of: depositing a field implant; depositing a wellimplant; and depositing an enhancement implant, wherein the steps ofdepositing a field implant, depositing a well implant, and depositing anenhancement implant are done using a single mask.
 22. The method ofclaim 21 wherein the well implant is an n-well implant.
 23. The methodof claim 21 wherein the well implant is a p-well implant.
 24. The methodof claim 21 further comprising the steps of: forming a high voltagenative transistor by blocking the well implant and the enhancementimplant; and offsetting the field implant from an active area of thenative transistor, thereby obtaining high gated-diode junction breakdowncharacteristics.
 25. The method of claim 21, further comprising the stepof implanting a pocket implant to improve a punch-through immunity. 26.The method of claim 21 further comprising the step of: depositing twopocket implants; and merging the pocket implants together by lateraldiffusion, whereby a channel doping profile from the pocket implantdiffusion exhibits reverse-short-channel effect.